As computer hardware and software technology continues to progress, the need for larger and faster mass storage devices for storing computer software and data continues to increase. Electronic databases and computer applications such as multimedia applications require large amounts of disk storage space. An axiom in the computer industry is that there is no such thing as enough memory and disk storage space.
To meet these ever increasing demands, hard disk drive developers continue to evolve and advance the technology. Some of the early disk drives had a maximum storage capacity of five megabytes and used fourteen inch platters, whereas today's hard disk drives are commonly over one gigabyte and use 3.5 inch platters. Correspondingly, advances in the amount of data stored per unit of area, or areal density, have dramatically accelerated. For example, in the 1980's, areal density increased about thirty percent per year while in the 1990's annual areal density increases have been around sixty percent. The cost per megabyte of a hard disk drive is inversely related to its areal density.
Mass storage device manufacturers strive to produce high speed hard disk drives with large data capacities at lower and lower costs. A high speed hard disk drive is one that can store and retrieve data at a fast rate. One aspect of increasing disk drive speed and capacity is to improve or increase the areal density. Areal density may be increased by improving the method of storing and retrieving data.
In general, mass storage devices, such as hard disk drives, include a magnetic storage media, such as rotating disks or platters, a spindle motor, read/write heads, an actuator, a pre-amplifier, a read channel, a write channel, a servo controller, and control circuitry to control the operation of the hard disk drive and to properly interface the hard disk drive to a host or system bus. The read channel, write channel, servo controller, and memory may all be implemented as one integrated circuit that is referred to as a data channel. The control circuitry often includes a microprocessor for executing control programs or instructions during the operation of the hard disk drive.
A hard disk drive (HDD) performs write and read operations when storing and retrieving data. A typical HDD performs a write operation by transferring data from a host interface to its control circuitry. The control circuitry then stores the data in a local dynamic random access memory (DRAM). A control circuitry processor schedules a series of events to allow the information to be transferred to the disk platters through a write channel. The control circuitry moves the read/write heads to the appropriate track and locates the appropriate sector of the track. A sector generally has a fixed data storage capacity, such as 512 bytes of user data per sector. Finally, the HDD control circuitry transfers the data from the DRAM to the located sector of the disk platter through the write channel. The write channel may encode the data so that the data can be more reliably retrieved.
In a read operation, the appropriate sector to be read is located and data that has been previously written to the disk is read. The read/write head senses the changes in the magnetic flux of the disk platter and generates a corresponding analog signal. The analog signal is known as an analog read signal or analog data signal. The read channel receives the analog data signal, conditions the signal, and detects "zeros" and "ones" from the signal. The read channel conditions the signal by amplifying the signal to an appropriate level using automatic gain control (AGC) techniques. The read channel then filters the signal, to eliminate unwanted high frequency noise, equalizes the channel, detects "zeros" and "ones" from the signal, and formats the binary data for the control circuitry. The binary or digital data is then transferred from the read channel to the control circuitry and is stored in the DRAM of the control circuitry. The processor then communicates to the host that data is ready to be transferred.
As the disk platters are moving, the read/write heads must align or stay on a particular track. This is accomplished by reading information from the disk called a servo wedge. Generally, each sector has a corresponding servo wedge. The servo wedge indicates the position of the heads. The data channel receives this position information so the servo controller can continue to properly position the heads on the track for read and write operations.
Traditional HDD read channels used a technique known as peak detection for extracting or detecting digital information from the analog information stored on the magnetic media. In this technique, the waveform is level detected and if the waveform level is above a threshold during a sampling window, the data is considered a "one." More recently, advanced techniques utilizing discrete time signal processing (DTSP) to reconstruct the original data written to the disk are being used in read channel electronics to improve areal density. In these techniques, the data is synchronously sampled using a data recovery clock. The sample is then processed through a series of mathematical manipulations using signal processing theory.
There are several types of synchronously sampled data (SSD) channels. Partial response, maximum likelihood (PRML); extended PRML (EPRML); enhanced, extended PRML (EEPRML); fixed delay tree search (FDTS); and decision feedback equalization (DFE) are several examples of different types of SSD channels using DTSP techniques. The maximum likelihood detection performed in several of these systems is usually performed by a Viterbi decoder implementing the Viterbi algorithm, named after Andrew Viterbi who developed it in 1967.
The SSD channel or read channel generally requires mixed-mode circuitry for performing a read operation. During a read operation, the circuitry receives an analog data signal from a preamplifier and amplifies the signal while performing automatic gain control (AGC) to amplify the signal to a known level. Continuous time filtering is performed to remove unwanted noise and to provide waveform shaping. The signal is sampled and equalized to provide an equalized, analog signal having discrete values in a sample data domain or discrete time domain. The equalized signal is then provided to a detector and a digital error estimation circuit. The detector analyzes the signal to provide a digital read signal, while the digital error estimation circuit estimates an error for use as a feedback signal in timing recovery and gain control. A deserializer circuit then converts the digital read signal from a serial format to a parallel format. In all SSD channels, the major goal during a read operation is to accurately retrieve the data with the lowest bit error rate (BER) in the highest noise environment. The SSD channel circuitry may be implemented on a single integrated circuit package that contains various input and output (I/O) pins.
Digital error estimation circuits convert the equalized, analog data signal from the analog domain to the digital domain before performing error calculations. The error corresponds to the difference between the actual discrete values of the equalized signal and a target value. The digital error estimation circuits use an analog-to-digital converter (ADC) to convert the equalized, analog signal from the analog domain to the digital domain. The ADC may be a relatively large ADC such as a six-bit flash ADC. A six-bit ADC uses at least sixty-four comparators to perform the conversion. The ADC circuitry creates several disadvantages and problems in an SSD channel. For example, to implement the ADC requires additional circuitry which increases the overall silicon and size of the SSD channel circuit. The additional circuitry also increases fabrication costs and power consumption. Power consumption is especially critical in portable or battery powered applications such as laptop or notebook computers.
The digital error estimation circuit having a large ADC also suffers the disadvantage of reducing overall HDD storage capacity. The additional circuitry needed to implement the large ADC generates circuit delays which reduce or limit the overall bandwidth of the SSD channel. This results in an HDD having a reduced areal density or storage capacity.